It has been found that, in order to create a high performance SiGe bipolar transistor, the Ge profile in those transistors has to have a rapidly increasing concentration, or “ramp”, from a low concentration in the vicinity of the emitter-base junction to a higher concentration (e.g. 20-30% mole fraction) within the neutral base of the device. An increase in the Ge concentration creates a change in the band structure of the crystal, which defines an electric field across a portion of the neutral base. This electric field substantially accelerates the carriers to cross the device in a short time, and thus improves the high frequency gain of the device.
Thus the need to improve switching speed has driven an increase in the ramp rate, in order to increase the electric field in the neutral base, accelerating the carriers to high velocity in as short a distance as possible. As is also well known, a second effect of the Ge at the emitter-base junction is to reduce the conduction band potential at that location, and thus increase the quantity of electrons injected from the emitter into the neutral base. This electron injection comprises the collector current, which is a quantity that needs to be well controlled so that the behavior of the bipolar device, and thus the performance of the circuit, is predictable. The complicating factor is that the emitter junction depth is variable with normal process variations (e.g., emitter and base dopant concentration variation, interface variability, and temperature repeatability and uniformity).
Relative to the Ge ramp, the process variations in the emitter-base junction depth result in variations in the Ge percentage at that junction location, and thus collector current is found to be variable. Because the dependence of collector current on Ge percentage is exponential, this effect is observed to be large (at least a range of +−50 percentage of the nominal value).
Thus there is a tradeoff. Higher Ge ramp rates increase the speed of the bipolar transistor, yet the same higher ramp rates increase the variability of the collector current in the device.
There remains a need for providing the designers an option to improve tolerance.
It is well known that performance may be traded off with collector avalanche and breakdown voltage through mask-selectable modifications in collector design on the same chip. Commonly, this is accomplished through implantation through or before the epitaxy layer, or blocking this implant with a photoresist layer. Other inventors have seen appropriate to form completely different base epitaxy regions on a chip, through mask-selectable regions of exposed single-crystal collector prior to epitaxy growth. The base epitaxy in such a solution includes different collector, base, and emitter regions. Such a solution has drawbacks of process complexity resulting from the multiple critical film growth, longer process times from the lengthy growth of relatively thick films, and process control issues resulting from the completely separate devices.